UCR



Philip Brisk: Publications


Chateau de Chillon, Switzerland                             Chateau de Chillon, Switzerland

Microfluidics

B. Crites, K. Kong, and P. Brisk
Diagonal Component Expansion for Flow-layer Placement of Flow-based Microfluidic Biochips
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 
Seoul, Korea, October 15-20, 2017
Accepted for publication; to appear in an upcoming issue of the ACM Transactions on Embedded Computing Systems (TECS)

W. Minhass, J. McDaniel, M. Raagaard, P. Brisk, P. Pop, and J. Madsen
Scheduling and Fluid Routing for Flow-based Microfluidic Laboratories-on-a-Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Accepted for publication; to appear

K. O'Neal, D. Grissom, and P. Brisk
Resource-Constrained Scheduling for Digital Microfluidic Biochips
ACM Journal of Emerging Technology in Computing Systems (JETC)
Accepted for publication; to appear

J. Wang, V. G. J. Rogers, P. Brisk, and W. H. Grover
MOPSA: A Microfluidics-optimized Particle Simulation Algorithm
Biomicrofluidics (BMF)
11(3):034121 (2017)
Paper

B. Crites, K. Kong, and P. Brisk
Diagonal Component Expansion for Flow-layer Placement of Flow-based Microfluidic Biochips
Poster / No Publication
54th Design Automation Conference (DAC), Work in Progress (WIP) Session
Austin, TX, USA, June 18-22, 2017
Poster

J. Potter, W. Grover, and P. Brisk 
Design Automation for Paper Microfluidics with Passive Flow Substrates

Great Lakes Symposium on VLSI (GLSVLSI)
Banff, Alberta, Canada, May 10-12, 2017, pp. 215-220
Paper   Slides

B. Crites, K. Kong, and P. Brisk 
Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving
Poster / Short Paper
Great Lakes Symposium on VLSI (GLSVLSI)
Banff, Alberta, Canada, May 10-12, 2017, pp. 459-462
Paper   Poster

J. McDaniel, W. Grover, and P. Brisk
The Case for Semi-automated Design of Microfluidic Very Large Scale Integration (mVLSI) Chips

Design Automation and Test in Europe (DATE)
Lausanne, Switzerland, March 27-31, 2017, pp. 1793-1798
Paper    Slides

S. Windh, C. Phung, D. Grissom, P. Pop, and P. Brisk
Performance Improvements and Congestion Reduction for Routing-based Synthesis for Digital Microfluidic Biochips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
36(1):41-54, January, 2017
Paper

J. McDaniel, Z. Zimmerman, D. Grissom, and P. Brisk
PCB Escape Routing and Layer Minimization for Digital Microfluidic Biochips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
36(1):69-82, January, 2017
Paper

J. Wang, P. Brisk, and W. Grover
Random Design of Microfluidics
Lab-on-a-Chip
16(21):4212-4219, October, 2016
Paper

C. Curtis and P. Brisk
Simulation of Feedback-driven PCR Assays on a 2D Electrowetting Array using a Domain-Specific High-level Biological Programming Language
Microelectronics Journal
148(1):110-116, December, 2015
Paper

J. McDaniel, B. Crites, W. Grover, and P. Brisk
Flow Layer Physical Design for Microfluidic Chips based on Monolithic Membrane Valves
IEEE Design & Test
32(6):51-59, December, 2015
Paper

D. Grissom, C. Curtis, S. Windh, C. Phung, N. Kumar, Z. Zimmerman, K. O'Neal, J. McDaniel, N. Liao, and P. Brisk
An Open-source Compiler and PCB Synthesis Tool for Digital Microfluidic Biochips
Integration: The VLSI Journal
51:169-193, September, 2015
Paper

J. McDaniel, B. Crites, C. Curtis, and P. Brisk
Design Automation for Flow-based Microfluidic Biochips
37th Annual International conference of the IEEE Engineering in Medicine and Biology Society.
Mini-Symposium: Continuous-Flow Biochips: Technology, Testing, and Design for Fault-Tolerance and Reliability
Milano, Italy, August 25-29, 2015 (1 page)
Paper    Slides

C. Jaress, P. Brisk, and D. Grissom
Rapid Online Fault Recovery for Cyber-physical Digital Microfluidic Biochips
IEEE VLSI Test Symposium (VTS)
Napa, CA, April 27-29, 2015, pp. 1-6
Paper   Slides

D. Grissom, J. McDaniel, and P. Brisk
Performance and Cost Analysis of NoC-inspired Virtual Topologies for Digital Microfluidic Biochips
International Symposium on Integrated Circuits (ISIC)
Singapore, December 10-12, 2014, pp. 352-355
Paper   Slides   Video Presentation

D. Grissom, J. McDaniel, and P. Brisk
A Low-cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
33(11):1657-1670, November, 2014
Paper

J. McDaniel, D. Grissom, and P. Brisk
Multi-terminal PCB Escape Routing for Digital Microfluidic Biochips using Negotiated Congestion
22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Playa Del Carmen, Mexico, October 6-8, 2014, pp. 219-224
Paper   Slides

J. McDaniel, B. Parker, and P. Brisk
Simulated Annealing-based Placement for Microfluidic Large Scale Integration (mLSI) Chips
22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Playa Del Carmen, Mexico, October 6-8, 2014, pp. 213-218
Paper   Slides

D. Grissom and P. Brisk
Software Control of Cyber-physical Laboratories-on-a-Chip
36th Annual International conference of the IEEE Engineering in Medicine and Biology Society. 
Mini-Symposium: Health Cyber-Physical Systems: Present Status and Future Directions II
Chicago, IL, USA, August 26-30, 2014 (1 page)
Paper   Slides

D. Grissom, C. Curtis, and P. Brisk
Interpreting Assays with Control Flow on Digital Microfluidic Biochips
ACM Journal on Emerging Technologies in Computing (JETC)
10(3): article #24, April, 2014
Paper

D. Grissom and P. Brisk
Fast Online Synthesis of Digital Microfluidic Biochips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
33(3):356-369, February, 2014
Paper

I. E. Araci and P. Brisk
Recent Developments in Microfluidic Large-scale Integration
Current Opinion in Biotechnology
25:60-68, February, 2014
Paper

J. Fiske, D. Grissom, and P. Brisk
Exploring Speed and Energy Tradeoffs in Droplet Transport for Cyber-Physical Digital Microfluidic Biochips
19th Asia and South Pacific Design Automation Conference (ASPDAC)
Singapore, January 21-23, 2014, pp. 231-237
Paper    Slides

J. McDaniel, C. Curtis, and P. Brisk
Automatic Synthesis of Microfluidic Large Scale Integration Chips from a Domain-Specific Language
IEEE Biomedical Circuits and Systems Conference (BioCAS)
Rotterdam, The Netherlands, October 31 - November 2, 2013, pp. 101-104
Paper    Slides

D. Grissom and P. Brisk
A Field-programmable Pin-constrained Digital Microfluidic Biochip
50th Design Automation Conference (DAC)
Austin, TX, USA, June 2-6, 2013, article #46
Paper    Slides

J. McDaniel, A. Baez, B. Crites, A. Tammewar, and P. Brisk
Design and Verification Tools for Continuous Fluid Flow-based Microfluidic Devices
18th Asia and South Pacific Design Automation Conference (ASPDAC)
Yokohama, Japan, January 22-25, 2013, pp. 219-224
Paper    Slides

D. Grissom, K. O'Neal, B. Preciado, H. Patel, R. Doherty, N. Liao, and P. Brisk
A Digital Microfluidic Biochip Synthesis Framework
20th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Santa Cruz, CA, USA, October 7-12, 2012, pp. 177-182
Paper    Slides

K. O'Neal, D. Grissom, and P. Brisk
Force-directed List Scheduling for Digital Microfluidic Biochips
20th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Santa Cruz, CA, USA, October 7-12, 2012, pp. 7-12
Paper    Slides

D. Grissom and P. Brisk
Fast Online Synthesis of Generally Programmable Digital Microfluidic Biochips
10th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Tampere, Finland, October 7-12, 2012, pp. 413-422
Paper    Slides

D. Grissom and P. Brisk
Path Scheduling on Digital Microfluidic Biochips
49th Design Automation Conference (DAC)
San Francisco, CA, USA, June 3-7, 2012, pp. 26-35
Paper    Slides    Poster

D. Grissom and P. Brisk
A High-Performance Online Assay Interpreter  for Digital Microfluidic Biochips
Poster / Short Paper
22nd Great Lakes Symposium on VLSI (GLS-VLSI)
Salt Lake City, Utah, USA, May 3-4, 2012, pp. 103-106
Paper    Poster

Extensible Processors

J. Tarango, E. Keogh, and P. Brisk
Accelerating the Dynamic Time Warping Distance Measure using Logarithmic Arithmetic
Invited Paper
48th Asilomar Conference on Signals, Systems and Computers
Pacific Grove, CA, November 2-5, 2014, pp. 404-408
Paper   Slides

T. Kluter, S. Burri, P. Brisk, E. Charbon, and P. Ienne
Virtual Ways: Low-cost Coherence for Instruction Set Extensions with Architecturally Visible Storage
ACM Transactions on Architecture and Code Optimization (TACO)
11(2): article #15, June, 2014
Paper

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for  Instruction Set Extensions
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
22(1):62-75, January, 2014
Paper

L. Chen, J. Tarango, T. Mitra, and P. Brisk
A Just-in-Time Customizable Processor
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 18-21, 2013, pp. 524-531
Paper    Slides

J. Tarango, E. Keogh, and P. Brisk
Instruction Set Extensions for Dynamic Time Warping
International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Montreal, Canada, September 29 -October 4, 2013.
Paper    Slides

M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne
Selective Flexibility: Creating Domain-specific Reconfigurable Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
32(5):681-694, May, 2013
Paper

M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne
Selective Flexibility: Breaking the Rigidity of Data Path Merging
Design Automation and Test in Europe (DATE)
Dresden, Germany, March 12-16, 2012, pp. 1543-1548
Paper    Slides

P. Brisk
Architecture and Design Automation for Application-Specific Processors

Invited Paper
9th IEEE International Conference on ASIC (ASICON)
Xiamen, China, October 25-28, 2011, pp. 1179-1182
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Fast, Nearly Optimal ISE Identification with I/O Serialization Through Maximal Clique Enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
29(3):341-354, March, 2010
Paper

T. Kluter, S. Burri, P. Brisk, E. Charbon, and P. Ienne
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Instruction Set Extensions
Best Paper Nominee

5th International Conference on High-Performance Architectures and Compilers (HiPEAC)
Pisa, Italy, January 25-27, 2010, pp. 126-140
Paper    Slides

N. Pothineni, P. Brisk, P. Ienne, A. Kumar, and K. Paul
A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors
15th Asia and South Pacific Design Automation Conference (ASPDAC)
Taipei, Taiwan, January 18-21, 2010, pp. 707-712
Paper    Slides

P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne
Memory Organization and Data Layout for Custom Instruction Set Extensions with Architecturally Visible Storage
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 2-5, 2009, pp. 689-696
Paper    Slides

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
Way Stealing: Cache-Assisted Automatic Instruction Set Extensions
HiPEAC Paper Award

46th Design Automation Conference (DAC)
San Francisco, CA, USA, July 26-31, 2009, pp. 31-36
Paper    Slides

M. Zuluaga, T. Kluter, P. Brisk, N. Topham, and P. Ienne
Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions
7th IEEE Symposium on Application-Specific Processors (SASP)
San Francisco, CA, USA, July 27-28, 2009, pp. 114-121
Paper    Slides

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
MPSoC Design Using Application-Specific Architecturally Visible Communication
4th International Conference on High-Performance Embedded Architecture and Compilers (HiPEAC)
Paphos, Cyprus, January 25-28, 2009, pp. 183-197
Paper    Slides

T. Kluter, P. Brisk, P. Ienne, and E. Charbon
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions
6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Atlanta, GA, USA, October 19-24, 2008, pp. 243-248
Paper    Slides    Poster

A. K. Verma, P. Brisk, and P. Ienne
Fast, Quasi-Optimal and Pipelined Instruction Set Extensions
13th Asia and South Pacific Design Automation Conference (ASPDAC)
Seoul, Korea, January 21-24, 2008, pp. 334-339
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Rethinking Custom ISE Identification: A New Processor-Agnostic Method
Best Paper Award

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, September 30 - October 3, 2007, pp. 125-134
Paper    Slides

P. Brisk and M. Sarrafzadeh
Datapath Synthesis
in P. Ienne and R. Leupers, eds.
Customizable Embedded Processors: Design Technologies and Applications
Elsevier, July 28, 2006
Purchase the book

P. Brisk, A. Kaplan, and M. Sarrafzadeh
Area Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs
41st Design Automation Conference (DAC)
San Diego, CA, USA, June 7-11, 2004, pp. 395-400
Paper    Slides

P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh
Instruction Generation and Regulary Extraction for Reconfigurable Processors
International Symposium on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Grenoble, France, October 8-11, 2002, pp. 262-269
Paper    Slides

Embedded Processors

A. Ranganathan, A. G. Bayrak, T. Kluter, E. Charbon, P. Ienne, and P. Brisk
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture
International Conference on Embedded Computer Systems: Architecture, Modeling, and Simulation (SAMOS XII)
Samos, Greece, July 16-19, 2012, pp. 120-127
Paper    Slides    Slides (PDF)

GPUs and GPU Applications

K. O'Neal, P. Brisk, Z. Waters, A. Abousamra and E. Shriver
GPU Performance estimation Using software Rasterization and Machine Learning 
International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Seoul, Korea, October 15-20, 2017
Accepted for publication; to appear in an upcoming issue of the ACM Transactions on Embedded Computing Systems (TECS)

K. O'Neal, P. Brisk, E. Shriver, and M. Kishinevsky
HALWPE Hardware-Assisted Light Weight Performance Estimation for GPUs
Best Paper Nominee

54th Design Automation Conference (DAC)
Austin, TX, USA, June 18-22, 2017
Paper    Slides    Poster

Y. Zhu, Z. Zimmerman, N. Shakibay Senobari, C-C M. Yeh, G. Funning, A. Mueen, P. Brisk and E. Keogh 
Matrix Profile II: Exploiting a Novel Algorithm and GPUs to break the one Hundred Million Barrier for Time Series Motifs and
 Joins
IEEE International Conference on Data Mining (ICDM)
Barcelona, Spain, December 12-15, 2016
Paper    Slides

FPGA Architecture

Y. O. M. Moctar, N. George, H. Parandeh-Afshar, P. Ienne, G. G. F. Lemieux, and P. Brisk
Reducing the Cost of Floating-point Mantissa Alignment and Normalization in FPGAs
20th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 22-24, 2012, pp. 255-264
Paper    Slides

H. Parandeh-Afshar, G. Zgheib, P. Brisk, and P. Ienne

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains
19th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 27 - March 1, 2011, pp. 237-246
Paper    Slides

H. Parandeh-Afshar, A. K. Verma, P. Brisk, and P. Ienne
Improving FPGA Performance for Carry-Save Arithmetic
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
18(4):578-590, April, 2010
Paper

H. Parandeh-Afshar, A. Cevrero, P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne
A Flexible DSP Block to Enhance FPGA Arithmetic Performance
International Conference on Field Programmable Technology (FPT)
Sydney, Australia, December 9-11, 2009, pp. 70-77
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
An FPGA Logic Cell Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2(3): article #19, September, 2009
Paper

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, H. S. A. Niaki,
C. Nicopoulos, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2(2): article #13, June 2009
Paper

H. S. A. Niaki, A. Cevrero, P. Brisk, C. Nicopoulos, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Design Space Exploration for Field Programmable Counter Arrays
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Atlanta, GA, USA, October 19-24, 2008, pp. 207-216
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
A Novel FPGA Logic Block for Improved Arithmetic Performance
16th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 24-26, 2008, pp. 171-180
Paper    Slides

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Architectural Improvement for Field Programmable Counter Arrays:
Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs

16th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 24-26, 2008, pp. 181-190
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and H. Parandeh-Afshar
Enhancing FPGA Performance for Arithmetic Circuits
Short Paper

44th Design Automation Conference (DAC)
San Diego, CA, USA, June 4-8, 2007, pp. 334-337
Paper    Slides

FPGA Mapping Algorithms

Y. O. M. Moctar, G. G. F. Lemieux, and P. Brisk
Fast and Memory-Efficient Routing Algorithms for FPGAs with Sparse Intra-cluster Routing Crossbars
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
34(12):1928-1941, December, 2015
Paper

B. Miller, F. Vahid, T. Givargis, and P. Brisk
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
7(4): article #10, January, 2015
Paper

Y. O. M. Moctar and P. Brisk
Parallel FPGA Routing based on the Operator Formulation
51st Design Automation Conference (DAC)
San Francisco, CA, June 1-5, 2014
Paper   Slides

Y. O. M. Moctar, G. G. F. Lemieux, and P. Brisk
Routing Algorithms for FPGAs with Sparse Intra-cluster Routing Crossbars
22nd International Conference on Field Programmable Logic and Applications (FPL)
Oslo, Norway, August 29-31, 2012, pp. 91-98
Paper    Slides

H. Parandeh-Afshar, A. Neogy, P. Brisk, and P. Ienne
Compressor Tree Synthesis on Commercial High-Performance FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
4(4): article #39, December, 2011
Paper

H. Parandeh-Afshar, G. Zgheib, P. Brisk, and P. Ienne
Routing Wire Optimization through Generic Synthesis on FPGA Carry Chains
20th International Workshop on Logic and Synthesis (IWLS)
La Jolla, CA, USA, June 3-5, 2011
Paper    Slides

H. Parandeh-Afshar, A. Neogy, P. Brisk, and P. Ienne
Improved Synthesis of Compressor Trees on FPGAs by a Hybrid and Systematic Design Approach
19th International Workshop on Logic and Synthesis (IWLS)
Irvine, CA, USA, June 18-20, 2010, pp. 193-200
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
Exploiting Fast Carry-Chains of FPGAs for Designing Compressor Trees
Michal Servit Best Paper Award

19th International Conference on Field-Programmable Logic and Applications (FPL)
Prague, Czech Republic, August 31 - September 2, 2009, pp. 242-249
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Design Automation and Test in Europe (DATE)
Munich, Germany, March 10-14, 2008, pp. 1256-1261
Paper    Slides

H. Paradeh-Afshar, P. Brisk, and P. Ienne
Efficient Synthesis of Compressor Trees on FPGAs
13th Asia and South Pacific Design Automation Conference (ASPDAC)
Seoul, Korea, January 21-24, 2008, pp. 138-143
Paper    Slides

Reconfigurable Computing

L. Josipovic, P. Brisk, and P. Ienne
From C to Elastic Circuits
Invited Paper 
51st Asilomar Conference on Signals, Systems and Computers
Pacific Grove, CA, October 29 - November 1, 2017
Accepted for publication; to appear

L. Josipovic, P. Brisk, and P. Ienne
An Out-of-Order Load-Store Queue for Spatial Computing
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Seoul, Korea, October 15-20, 2017
Accepted for publication; to appear in an upcoming issue of the ACM Transactions on Embedded Computing Systems (TECS)

S. K. Shukla, Y. Yang, L. N. Bhuyan, and P. Brisk
Shared Memory Heterogeneous Computation on PCIe-Supported Platforms
Poster / Short Paper
23rd International Conference on Field Programmable Logic and Applications (FPL)
Porto, Portugal, September 2-4, 2013
Paper

A. Nahapetian, P. Brisk, S. Ghiasi, and M. Sarrafzadeh
An Approximation Algorithm for Scheduling on Heterogeneous Reconfigurable Resources
ACM Transactions on Embedded Computing Systems (TECS)
9(1): article #5, October, 2009
Paper

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne
Using 3D Integration Technology to Realize Multi-Context FPGAs
Poster / Short Paper

19th International Conference on Field-Programmable Logic and Applications (FPL)
Prague, Czech Republic, August 31 - September 2, 2009 pp. 507-510
Paper    Poster

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne
3D Configuration Caching for 2D FPGAs
Poster / Abstract Only

17th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 22-24, 2009, pp. 286
Poster

Register Allocation

B. Boissinot, P. Brisk, A. Darte, and F. Rastello
SSI Properties Revisited
ACM Transactions on Embedded Computing Systems (TECS)
Special Issue on Software and Compilers for Embedded Systems

11S(1): article #21, June, 2012
Paper

Q. Columbet, B. Boissinot, P. Brisk, S. Hack, and F. Rastello
Graph-Coloring and Treescan Register Allocation Using Repairing
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Taipei, Taiwan, October 9-14, 2011, pp. 45-54
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High-Level Synthesis Using SSA Form
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
29(7):1096-1009, July, 2010
Paper

B. Boissinot, P. Brisk, A. Darte, and F. Rastello
SSI Revisited
Technical Report LIP-2009-24, ENS-Lyon
July 25, 2009
Paper

P. Brisk, A. K. Verma, and P. Ienne
Optimistic Chordal Coloring: A Coalescing Heuristic for SSA Form Programs
Springer Journal on Design Automation for Embedded Systems (DAEM)
Special Issue: Embedded Systems Week 2007

13(1-2):115-137, June, 2009
Paper

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis and ASIP Design
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 5-8, 2007, pp. 172-179
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, September 30 - October 3, 2007, pp. 209-217
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis Using SSA Form
16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and M. Sarrafzadeh
Interconnect Optimization for High-Level Synthesis of Static Single Assignment Form Programs
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Static Single Assignment Form and the Dominance Relation
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Interference Graphs for Procedures in Static Single Information Form are Interval Graphs
10th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Nice, France, April 20, 2007, pp. 101-110
Paper    Slides

P. Brisk, F. Dabiri, R. Jafari, and M. Sarrafzadeh
Optimal Register Sharing for High-Level Synthesis of SSA Form Programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
25(5):772-779, May, 2006
Paper

P. Brisk, F. Dabiri, J. Macbeth, and M. Sarrafzadeh
Polynomial-Time Graph Coloring Register Allocation
14th International Workshop on Logic and Synthesis (IWLS)
Lake Arrowhead, CA, USA, June 8-10, 2005

Logic Synthesis

A. K. Verma, P. Brisk, and P. Ienne
Iterative Layering: Optimizing Arithmetic Circuits By Structuring the Information Flow
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 2-5, 2009, pp. 797-804
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
A Decomposition Algorithm to Structure Arithmetic Circuits
18th International Workshop on Logic and Synthesis (IWLS)
Berkeley, CA, USA, July 31 - August 2, 2009
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Challenges in Automatic Optimization of Arithmetic Circuits
Invited Paper

19th IEEE Symposium on Computer Arithmetic (ARITH-19)
Portland, OR, USA, June 8-10, 2009, pp. 213-218
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
XP2: A New compact Representation for Manipulating Arithmetic Circuits
17th International Workshop on Logic and Synthesis (IWLS)
Lake Tahoe, CA, USA, June 4-6, 2008
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Best Paper Nominee

44th Design Automation Conference (DAC)
San Diego, CA, USA, June 4-8, 2007, pp. 404-409
Paper    Slides

High-Level Synthesis

P. Brisk and P. Ienne
On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis
Poster / Full Paper

International Symposium on VLSI Design Automation and Test (VLSI-DAT)
Hsinchu, Taiwan, April 28-30, 2009, pp. 339-342
Paper    Poster

A. K. Verma, P. Brisk, and P. Ienne
Dataflow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
27(10):1761-1774, October 2008
Paper

R. Kastner, W. Gong, X. Hau, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh
Layout Driven Data Communication Optimization for High-Level Synthesis
Design Automation and Test in Europe (DATE)
Munich, Germany, March 6-10, 2006, pp. 1185-1190
Paper    Slides

R. Kastner, W. Gong, X. Hau, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh
Physically Aware Data Communication Optimization for Hardware Synthesis
14th International Workshop on Logic and Synthesis (IWLS)
Lake Arrowhead, CA, USA, June 8-10, 2005
Paper    Slides

A. Kaplan, P. Brisk, and R. Kastner
Data Communication Estimation and Reduction for Reconfigurable Systems
40th ACM/IEEE Design Automation Conference (DAC)
Anaheim, CA, USA, June 2-6, 2003, pp. 616-621
Paper    Slides\

Video Processing

J. Boutellier, A. Cevrero, P. Brisk, and P. Ienne
Architectural Support for the Orchestration of Fine-Grained Multiprocessing for Portable Streaming Applications
IEEE Workshop on Signal Processing Systems (SiPS)
Tampere, Finland, October 7-9, 2009, pp. 115-120
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
Scalable and Low Cost Design Approach for Variable Block Size Motion Estimation (VBSME)
International Symposium on VLSI Design Automation and Test (VLSI-DAT)
Hsinchu, Taiwan, April 28-30, 2009, pp. 271-274
Paper    Slides

J. Boutellier, P. Brisk, and P. Ienne
Insights to Variable Block Size Motion Estimation by Design Space Exploration
Poster / Full Paper

Conference on Design and Architectures for Signal and Image Processing (DASIP)
Brussels, Belgium, November 24-26, 2008, pp. 307-313
Paper    Poster

J. Boutellier, V. Sadhanala, C. Lucarz, P. Brisk, and M. Mattavelli
Scheduling of Dataflow Models within the Reconfigurable Video Coding Framework
Poster / Full Paper

IEEE Workshop on Signal Processing Systems (SiPS)
Washington D. C., USA, October 8-10, 2008, pp. 182-187
Paper    Poster

Computer Arithmetic

S. Boroumand, H. P. Afshar, P. Brisk and S. Mohammadi
CAL: Exploring Cost, Accuracy, and Latency in Approximate and Speculative Adder Design
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Cambridge, UK, October 23-25, 2017
Accepted for publication; to appear

A. Verma, A. K. Verma, H. Parandeh-Afshar, P. Brisk, and P. Ienne
Synthesis of Floating-point Addition Clusters on FPGAs Using Carry-save Arithmetic
Poster / Short Paper

20th International Conference on Field-Programmable Logic and Applications (FPL)
Milan, Italy, August 31 - September 2, 2010, pp. 19-24
Paper    Poster

A. K. Verma, Y. Zhu, P. Brisk, and P. Ienne
Arithmetic Optimization for Custom Instruction Set Synthesis
Poster / Short Paper

7th IEEE Symposium on Application-Specific Processors (SASP)
San Francisco, CA, USA, July 27-28, 2009, pp. 54-57
Paper    Poster

A. Paidimarri, A. Cevrero, P. Brisk, and P. Ienne
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation
Poster / Short Paper
HiPEAC Paper Award

17th IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
Napa, CA, USA, April 5-7, 2009, pp. 267-270
Paper    Poster

A. Verma, A. K. Verma, P. Brisk, and P. Ienne
Hybrid LZA: A Near Optimal Implementation of the Leading Zero Anticipator
14th Asia and South Pacific Design Automation Conference (ASPDAC)
Yokohama, Japan, January 19-22, 2009, pp. 203-209
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design
Design Automation and Test in Europe (DATE)
Munich, Germany, March 10-14, 2008, pp. 1250-1255
Paper    Slides

Medical Systems

T. Massey, F. Dabiri, R. Jafari, H. Noshadi, P. Brisk, and M. Sarrafzadeh
Reconfigurable Medical Embedded Systems
in A. Lazakidou and K. Siassiakos, eds.
Handbook of Research on Distributed Medical Informatics and E-Health
IGI Global, August 22, 2008
Purchase the book

T. Massey, F. Dabiri, R. Jafari, H. Noshadi, P. Brisk, and M. Sarrafzadeh
Towards Reconfigurable Medical Embedded Systems
Workshop on High Confidence Medical Devices, Software and Systems, and Medical Device Plug-and-Play Interoperability
(HCMDSS-MDPnP)

Boston, MA, USA, June 25-27, 2007, pp. 178-180
Paper

R. Jafari, F. Dabiri, P. Brisk, and M. Sarrafzadeh
Adaptive and Fault Tolerant Medical Vest for Life-Critical Medical Monitoring
20th ACM Symposium on Applied Computing (SAC)
Santa Fe, NM, USA, March 13-17, 2005, pp. 272-279
Paper

Security

A. Becker, W. Hu, Y. Tai, P. Brisk, R. Kastner, and P. Ienne
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking
54th Design Automation Conference (DAC)
Austin, TX, USA, June 18-22, 2017
Paper    Slides    Poster

A. G. Bayrak, F. Regazzoni, D. Novo Bruna, P. Brisk, F-X. Standaert, and P. Ienne
Automatic Application of Power Analysis Countermeasures
IEEE Transactions on Computers
64(2):329-341, February, 2015
Paper

A. G. Bayrak, N. Velickovic, F. Regazzoni, D. Novo, P. Brisk and P. Ienne
An EDA-Friendly Protection Scheme against Side-Channel Attacks
Design Automation and Test in Europe (DATE)
Grenoble, France, March 18-22, 2013, pp. 410-415
Paper    Slides

A. G. Bayrak, F. Regazzoni, P. Brisk, F-X. Standaert, and P. Ienne
A First Step Towards Automatic Application of Power Analysis Countermeasures
48th Design Automation Conference (DAC)
San Diego, CA, USA, June 5-9, 2011, pp. 230-235
Paper    Slides

F. Regazzoni, A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Workshop on Crytographic Hardware and Embedded Systems (CHES)
Lausanne, Switzerland, September 6-9, 2009, pp. 205-219
Paper    Slides

T. Massey, P. Brisk, F. Dabiri, and M. Sarrafzadeh
Delay Aware Reconfigurable Security for Embedded Systems
2nd ICST International Conference on Body-Area Networks (Bodynets)
Florence, Italy, June 11-13, 2007, article no. 12
Paper    Slides

P. Brisk, A. Kaplan, and M. Sarrafzadeh
Parallel Analysis of the Rijndael Block Cipher
IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS)
Marina Del Rey, CA, USA, November 3-5, 2003
Paper    Slides

Code Compression

P. Brisk, J. Macbeth, A. Nahapetian, and M. Sarrafzadeh
A Dictionary Construction Technique for Code Compression Systems with Echo Instructions
ACM/SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)
Chicago, IL, USA, June 15-17, 2005, pp. 105-114
Paper    Slides

P. Brisk, A. Nahapetian, and M. Sarrafzadeh
Instruction Selection for Compilers that Target Architectures with Echo Instructions
8th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Amsterdam, The Netherlands, September 2-4, 2004, pp. 229-243
Paper    Slides

P. Brisk and M. Sarrafzadeh
Framework and Design Methodology for a Compiler that Compresses Code Using Echo Instructions
2nd Workshop on Optimization for DSP and Embedded Systems (ODES-2)
co-located with the International Symposium on Code Generation and Optimization (CGO)
Palo Alto, CA, USA, March 21, 2004
Slides

Wild and Crazy Ideas

J. L. Ayala, D. Atienza, and P. Brisk
Thermal-Aware Data Flow Analysis
Wild and Crazy Idea (WACI) / Short Paper

46th Design Automation Conference (DAC)
San Francisco, CA, USA, July 26-31, 2009, pp. 613-614
Paper    Slides


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