UCR



Philip Brisk: Computer Arithmetic


Lausanne, Switzerland                                                                          Lausanne, Switzerland

Computer Arithmetic

S. Boroumand, H. P. Afshar, P. Brisk and S. Mohammadi
CAL: Exploring Cost, Accuracy, and Latency in Approximate and Speculative Adder Design
30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Cambridge, UK, October 23-25, 2017
Accepted for publication; to appear

A. Verma, A. K. Verma, H. Parandeh-Afshar, P. Brisk, and P. Ienne
Synthesis of Floating-point Addition Clusters on FPGAs Using Carry-save Arithmetic
Poster / Short Paper

20th International Conference on Field-Programmable Logic and Applications (FPL)
Milan, Italy, August 31 - September 2, 2010, pp. 19-24
Paper    Poster

A. K. Verma, Y. Zhu, P. Brisk, and P. Ienne
Arithmetic Optimization for Custom Instruction Set Synthesis
Poster / Short Paper

7th IEEE Symposium on Application-Specific Processors (SASP)
San Francisco, CA, USA, July 27-28, 2009, pp. 54-57
Paper    Poster

A. Paidimarri, A. Cevrero, P. Brisk, and P. Ienne
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation
Poster / Short Paper
HiPEAC Paper Award

17th IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
Napa, CA, USA, April 5-7, 2009, pp. 267-270
Paper    Poster

A. Verma, A. K. Verma, P. Brisk, and P. Ienne
Hybrid LZA: A Near Optimal Implementation of the Leading Zero Anticipator
14th Asia and South Pacific Design Automation Conference (ASPDAC)
Yokohama, Japan, January 19-22, 2009, pp. 203-209
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design
Design Automation and Test in Europe (DATE)
Munich, Germany, March 10-14, 2008, pp. 1250-1255
Paper    Slides


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