UCR



Philip Brisk: Extensible Processors


Fountain, Palma di Mallorca                             Yverdon Les Bains, Switzerland

Extensible Processors

J. Tarango, E. Keogh, and P. Brisk
Accelerating the Dynamic Time Warping Distance Measure using Logarithmic Arithmetic
Invited Paper
48th Asilomar Conference on Signals, Systems and Computers
Pacific Grove, CA, November 2-5, 2014, pp. 404-408
Paper   Slides

T. Kluter, S. Burri, P. Brisk, E. Charbon, and P. Ienne
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage
ACM Transactions on Architecture and Code Optimization (TACO)
11(2): article #15, June, 2014
Paper

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for  Instruction Set Extensions
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
22(1):62-75, January, 2014
Paper

L. Chen, J. Tarango, T. Mitra, and P. Brisk
A Just-in-Time Customizable Processor
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 18-21, 2013, pp. 524-531
Paper    Slides

J. Tarango, E. Keogh, and P. Brisk
Instruction Set Extensions for Dynamic Time Warping
International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Montreal, Canada, September 29 -October 4, 2013.
Paper    Slides

M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne
Selective Flexibility: Creating Domain-specific Reconfigurable Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
32(5):681-694, May, 2013
Paper

M. Stojilovic, D. Novo, L. Saranovac, P. Brisk, and P. Ienne
Selective Flexibility: Breaking the Rigidity of Data Path Merging
Design Automation and Test in Europe (DATE)
Dresden, Germany, March 12-16, 2012, pp. 1543-1548
Paper    Slides

P. Brisk
Architecture and Design Automation for Application-Specific Processors

Invited Paper
9th IEEE International Conference on ASIC (ASICON)
Xiamen, China, October 25-28, 2011, pp. 1179-1182
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Fast, Nearly Optimal ISE Identification with I/O Serialization Through Maximal Clique Enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
29(3):341-354, March, 2010
Paper

T. Kluter, S. Burri, P. Brisk, E. Charbon, and P. Ienne
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Instruction Set Extensions
Best Paper Nominee

5th International Conference on High-Performance Architectures and Compilers (HiPEAC)
Pisa, Italy, January 25-27, 2010, pp. 126-140
Paper    Slides

N. Pothineni, P. Brisk, P. Ienne, A. Kumar, and K. Paul
A High-Level Synthesis Flow for Custom Instruction Set Extensions for Application-Specific Processors
15th Asia and South Pacific Design Automation Conference (ASPDAC)
Taipei, Taiwan, January 18-21, 2010, pp. 707-712
Paper    Slides

P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne
Memory Organization and Data Layout for Custom Instruction Set Extensions with Architecturally Visible Storage
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 2-5, 2009, pp. 689-696
Paper    Slides

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
Way Stealing: Cache-Assisted Automatic Instruction Set Extensions
HiPEAC Paper Award

46th Design Automation Conference (DAC)
San Francisco, CA, USA, July 26-31, 2009, pp. 31-36
Paper    Slides

M. Zuluaga, T. Kluter, P. Brisk, N. Topham, and P. Ienne
Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions
7th IEEE Symposium on Application-Specific Processors (SASP)
San Francisco, CA, USA, July 27-28, 2009, pp. 114-121
Paper    Slides

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
MPSoC Design Using Application-Specific Architecturally Visible Communication
4th International Conference on High-Performance Embedded Architecture and Compilers (HiPEAC)
Paphos, Cyprus, January 25-28, 2009, pp. 183-197
Paper    Slides

T. Kluter, P. Brisk, P. Ienne, and E. Charbon
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions
6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Atlanta, GA, USA, October 19-24, 2008, pp. 243-248
Paper    Slides    Poster

A. K. Verma, P. Brisk, and P. Ienne
Fast, Quasi-Optimal and Pipelined Instruction Set Extensions
13th Asia and South Pacific Design Automation Conference (ASPDAC)
Seoul, Korea, January 21-24, 2008, pp. 334-339
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Rethinking Custom ISE Identification: A New Processor-Agnostic Method
Best Paper Award

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, September 30 - October 3, 2007, pp. 125-134
Paper    Slides

P. Brisk and M. Sarrafzadeh
Datapath Synthesis
in P. Ienne and R. Leupers, eds.
Customizable Embedded Processors: Design Technologies and Applications
Elsevier, July 28, 2006
Purchase the book

P. Brisk, A. Kaplan, and M. Sarrafzadeh
Area Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs
41st Design Automation Conference (DAC)
San Diego, CA, USA, June 7-11, 2004, pp. 395-400
Paper    Slides

P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh
Instruction Generation and Regulary Extraction for Reconfigurable Processors
International Symposium on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Grenoble, France, October 8-11, 2002, pp. 262-269
Paper    Slides


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