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Philip Brisk: FPGA Architecture


California Coast                             California Coast

FPGA Architecture

Y. O. M. Moctar, N. George, H. Parandeh-Afshar, P. Ienne, G. G. F. Lemieux, and P. Brisk
Reducing the Cost of Floating-point Mantissa Alignment and Normalization in FPGAs
20th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 22-24, 2012, pp. 255-264
Paper    Slides

H. Parandeh-Afshar, G. Zgheib, P. Brisk, and P. Ienne

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains
19th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 27 - March 1, 2011, pp. 237-246
Paper    Slides

H. Parandeh-Afshar, A. K. Verma, P. Brisk, and P. Ienne
Improving FPGA Performance for Carry-Save Arithmetic
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
18(4):578-590, April, 2010
Paper

H. Parandeh-Afshar, A. Cevrero, P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne
A Flexible DSP Block to Enhance FPGA Arithmetic Performance
International Conference on Field Programmable Technology (FPT)
Sydney, Australia, December 9-11, 2009, pp. 70-77
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
An FPGA Logic Cell Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2(3): article #19, September, 2009
Paper

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, H. S. A. Niaki,
C. Nicopoulos, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2(2): article #13, June 2009
Paper

H. S. A. Niaki, A. Cevrero, P. Brisk, C. Nicopoulos, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Design Space Exploration for Field Programmable Counter Arrays
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Atlanta, GA, USA, October 19-24, 2008, pp. 207-216
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
A Novel FPGA Logic Block for Improved Arithmetic Performance
16th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 24-26, 2008, pp. 171-180
Paper    Slides

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Architectural Improvement for Field Programmable Counter Arrays:
Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs

16th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 24-26, 2008, pp. 181-190
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and H. Parandeh-Afshar
Enhancing FPGA Performance for Arithmetic Circuits
Short Paper

44th Design Automation Conference (DAC)
San Diego, CA, USA, June 4-8, 2007, pp. 334-337
Paper    Slides


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