Philip Brisk: High-Level Synthesis

Statue                                                                          18 Mile Drive, CA

High-Level Synthesis

P. Brisk and P. Ienne
On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis
Poster / Full Paper

International Symposium on VLSI Design Automation and Test (VLSI-DAT)
Hsinchu, Taiwan, April 28-30, 2009, pp. 339-342
Paper    Poster

A. K. Verma, P. Brisk, and P. Ienne
Dataflow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
27(10):1761-1774, October 2008

R. Kastner, W. Gong, X. Hau, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh
Layout Driven Data Communication Optimization for High-Level Synthesis
Design Automation and Test in Europe (DATE)
Munich, Germany, March 6-10, 2006, pp. 1185-1190
Paper    Slides

R. Kastner, W. Gong, X. Hau, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh
Physically Aware Data Communication Optimization for Hardware Synthesis
14th International Workshop on Logic and Synthesis (IWLS)
Lake Arrowhead, CA, USA, June 8-10, 2005
Paper    Slides

A. Kaplan, P. Brisk, and R. Kastner
Data Communication Estimation and Reduction for Reconfigurable Systems
40th ACM/IEEE Design Automation Conference (DAC)
Anaheim, CA, USA, June 2-6, 2003, pp. 616-621
Paper    Slides

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