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Philip Brisk: Logic Synthesis


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Logic Synthesis

A. K. Verma, P. Brisk, and P. Ienne
Iterative Layering: Optimizing Arithmetic Circuits By Structuring the Information Flow
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 2-5, 2009, pp. 797-804
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
A Decomposition Algorithm to Structure Arithmetic Circuits
18th International Workshop on Logic and Synthesis (IWLS)
Berkeley, CA, USA, July 31 - August 2, 2009
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Challenges in Automatic Optimization of Arithmetic Circuits
Invited Paper

19th IEEE Symposium on Computer Arithmetic (ARITH-19)
Portland, OR, USA, June 8-10, 2009, pp. 213-218
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
XP2: A New compact Representation for Manipulating Arithmetic Circuits
17th International Workshop on Logic and Synthesis (IWLS)
Lake Tahoe, CA, USA, June 4-6, 2008
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Best Paper Nominee

44th Design Automation Conference (DAC)
San Diego, CA, USA, June 4-8, 2007, pp. 404-409
Paper    Slides


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