UCR



Philip Brisk: Register Allocation


Chateau de Chillon, Switzerland                                                                          Chateau de Chillon, Switzerland

Register Allocation

B. Boissinot, P. Brisk, A. Darte, and F. Rastello
SSI Properties Revisited
ACM Transactions on Embedded Computing Systems (TECS)
Special Issue on Software and Compilers for Embedded Systems

11S(1): article #21, June, 2012
Paper

Q. Columbet, B. Boissinot, P. Brisk, S. Hack, and F. Rastello
Graph-Coloring and Treescan Register Allocation Using Repairing
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Taipei, Taiwan, October 9-14, 2011, pp. 45-54
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High-Level Synthesis Using SSA Form
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
29(7):1096-1109, July, 2010
Paper

B. Boissinot, P. Brisk, A. Darte, and F. Rastello
SSI Revisited
Technical Report LIP-2009-24, ENS-Lyon
July 25, 2009
Paper

P. Brisk, A. K. Verma, and P. Ienne
Optimistic Chordal Coloring: A Coalescing Heuristic for SSA Form Programs
Springer Journal on Design Automation for Embedded Systems (DAEM)
Special Issue: Embedded Systems Week 2007

13(1-2):115-137, June, 2009
Paper

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis and ASIP Design
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 5-8, 2007, pp. 172-179
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, September 30 - October 3, 2007, pp. 209-217
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis Using SSA Form
16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and M. Sarrafzadeh
Interconnect Optimization for High-Level Synthesis of Static Single Assignment Form Programs
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Static Single Assignment Form and the Dominance Relation
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Interference Graphs for Procedures in Static Single Information Form are Interval Graphs
10th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Nice, France, April 20, 2007, pp. 101-110
Paper    Slides

P. Brisk, F. Dabiri, R. Jafari, and M. Sarrafzadeh
Optimal Register Sharing for High-Level Synthesis of SSA Form Programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
25(5):772-779, May, 2006
Paper

P. Brisk, F. Dabiri, J. Macbeth, and M. Sarrafzadeh
Polynomial-Time Graph Coloring Register Allocation
14th International Workshop on Logic and Synthesis (IWLS)
Lake Arrowhead, CA, USA, June 8-10, 2005


More Information

General Campus Information

University of California, Riverside
900 University Ave.
Riverside, CA 92521
Tel: (951) 827-1012

Career OpportunitiesUCR Libraries
Campus StatusDirections to UCR

College Information

Bourns College of Engineering
Bourns Hall

Tel: (951) 827-5190
Fax: (951) 827-3188
E-mail: systems@cs.ucr.edu

Related Links

Footer