UCR



Philip Brisk: Workshop Papers and Abstract-only Posters


Tree, Great South Gate, Tainan, Taiwan                                                                          18 Mile Drive, CA

Workshop Papers and Abstract-only Posters.

B. Crites, K. Kong, and P. Brisk
Diagonal Component Expansion for Flow-layer Placement of Flow-based Microfluidic Biochips
Poster / No Publication
54th Design Automation Conference (DAC), Work in Progress (WIP) Session
Austin, TX, USA, June 18-22, 2017
Poster

H. Parandeh-Afshar, G. Zgheib, P. Brisk, and P. Ienne
Routing Wire Optimization through Generic Synthesis on FPGA Carry Chains
20th International Workshop on Logic and Synthesis (IWLS)
La Jolla, CA, USA, June 3-5, 2011
Paper    Slides

H. Parandeh-Afshar, A. Neogy, P. Brisk, and P. Ienne
Improved Synthesis of Compressor Trees on FPGAs by a Hybrid and Systematic Design Approach
19th International Workshop on Logic and Synthesis (IWLS)
Irvine, CA, USA, June 18-20, 2010, pp. 193-200
Paper    Slides

J. Boutellier, A. Cevrero, P. Brisk, and P. Ienne
Architectural Support for the Orchestration of Fine-Grained Multiprocessing for Portable Streaming Applications
IEEE Workshop on Signal Processing Systems (SiPS)
Tampere, Finland, October 7-9, 2009, pp. 115-120
Paper    Slides

F. Regazzoni, A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Workshop on Crytographic Hardware and Embedded Systems (CHES)
Lausanne, Switzerland, September 6-9, 2009, pp. 205-219
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
A Decomposition Algorithm to Structure Arithmetic Circuits
18th International Workshop on Logic and Synthesis (IWLS)
Berkeley, CA, USA, July 31 - August 2, 2009
Paper    Slides

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne
3D Configuration Caching for 2D FPGAs
Poster / Abstract Only

17th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 22-24, 2009, pp. 286
Poster

J. Boutellier, V. Sadhanala, C. Lucarz, P. Brisk, and M. Mattavelli
Scheduling of Dataflow Models within the Reconfigurable Video Coding Framework
Poster / Full Paper

IEEE Workshop on Signal Processing Systems (SiPS)
Washington D. C., USA, October 8-10, 2008, pp. 182-187
Paper    Poster

A. K. Verma, P. Brisk, and P. Ienne
XP2: A New compact Representation for Manipulating Arithmetic Circuits
17th International Workshop on Logic and Synthesis (IWLS)
Lake Tahoe, CA, USA, June 4-6, 2008
Paper    Slides

T. Massey, F. Dabiri, R. Jafari, H. Noshadi, P. Brisk, and M. Sarrafzadeh
Towards Reconfigurable Medical Embedded Systems
Workshop on High Confidence Medical Devices, Software and Systems, and Medical Device Plug-and-Play Interoperability
(HCMDSS-MDPnP)

Boston, MA, USA, June 25-27, 2007, pp. 178-180
Paper

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis Using SSA Form
16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and M. Sarrafzadeh
Interconnect Optimization for High-Level Synthesis of Static Single Assignment Form Programs
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Static Single Assignment Form and the Dominance Relation
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Interference Graphs for Procedures in Static Single Information Form are Interval Graphs
10th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Nice, France, April 20, 2007, pp. 101-110
Paper    Slides

P. Brisk, F. Dabiri, J. Macbeth, and M. Sarrafzadeh
Polynomial-Time Graph Coloring Register Allocation
14th International Workshop on Logic and Synthesis (IWLS)
Lake Arrowhead, CA, USA, June 8-10, 2005

R. Kastner, W. Gong, X. Hau, F. Brewer, A. Kaplan, P. Brisk, and M. Sarrafzadeh
Physically Aware Data Communication Optimization for Hardware Synthesis
14th International Workshop on Logic and Synthesis (IWLS)
Lake Arrowhead, CA, USA, June 8-10, 2005
Paper    Slides

P. Brisk, A. Nahapetian, and M. Sarrafzadeh
Instruction Selection for Compilers that Target Architectures with Echo Instructions
8th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Amsterdam, The Netherlands, September 2-4, 2004, pp. 229-243
Paper    Slides

P. Brisk and M. Sarrafzadeh
Framework and Design Methodology for a Compiler that Compresses Code Using Echo Instructions
2nd Workshop on Optimization for DSP and Embedded Systems (ODES-2)
co-located with the International Symposium on Code Generation and Optimization (CGO)
Palo Alto, CA, USA, March 21, 2004
Slides


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