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Philip Brisk: 2007 Publications


Waterfall, Chihkan Towers, Tainan, Taiwan                             Garden, Koxinga's Shrine, Tainan Taiwan

2007

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis and ASIP Design
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 5-8, 2007, pp. 172-179
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Rethinking Custom ISE Identification: A New Processor-Agnostic Method
Best Paper Award

International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, September 30 - October 3, 2007, pp. 125-134
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Salzburg, Austria, September 30 - October 3, 2007, pp. 209-217
Paper    Slides

T. Massey, F. Dabiri, R. Jafari, H. Noshadi, P. Brisk, and M. Sarrafzadeh
Towards Reconfigurable Medical Embedded Systems
Workshop on High Confidence Medical Devices, Software and Systems, and Medical Device Plug-and-Play Interoperability
(HCMDSS-MDPnP)

Boston, MA, USA, June 25-27, 2007, pp. 178-180
Paper

T. Massey, P. Brisk, F. Dabiri, and M. Sarrafzadeh
Delay Aware Reconfigurable Security for Embedded Systems
2nd ICST International Conference on Body-Area Networks (Bodynets)
Florence, Italy, June 11-13, 2007, article no. 12
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Best Paper Nominee

44th Design Automation Conference (DAC)
San Diego, CA, USA, June 4-8, 2007, pp. 404-409
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and H. Parandeh-Afshar
Enhancing FPGA Performance for Arithmetic Circuits
Short Paper

44th Design Automation Conference (DAC)
San Diego, CA, USA, June 4-8, 2007, pp. 334-337
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
Optimal Polynomial-Time Interprocedural Register Allocation for High-Level Synthesis Using SSA Form
16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Slides

P. Brisk, A. K. Verma, P. Ienne, and M. Sarrafzadeh
Interconnect Optimization for High-Level Synthesis of Static Single Assignment Form Programs
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Static Single Assignment Form and the Dominance Relation
Poster / Full Paper

16th International Workshop on Logic and Synthesis (IWLS)
San Diego, CA, USA, May 30 - June 1, 2007
Paper    Poster

P. Brisk and M. Sarrafzadeh
Interference Graphs for Procedures in Static Single Information Form are Interval Graphs
10th International Workshop on Software and Compilers for Embedded Systems (SCOPES)
Nice, France, April 20, 2007, pp. 101-110
Paper    Slides


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