UCR



Philip Brisk: 2008 Publications


18 Mile Drive, CA                                                                          18 Mile Drive, CA

2008

J. Boutellier, P. Brisk, and P. Ienne
Insights to Variable Block Size Motion Estimation by Design Space Exploration
Poster / Full Paper

Conference on Design and Architectures for Signal and Image Processing (DASIP)
Brussels, Belgium, November 24-26, 2008, pp. 307-313
Paper    Poster

T. Kluter, P. Brisk, P. Ienne, and E. Charbon
Speculative DMA for Architecturally Visible Storage in Instruction Set Extensions
6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS)
Atlanta, GA, USA, October 19-24, 2008, pp. 243-248
Paper    Slides     Poster

H. S. A. Niaki, A. Cevrero, P. Brisk, C. Nicopoulos, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Design Space Exploration for Field Programmable Counter Arrays
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Atlanta, GA, USA, October 19-24, 2008, pp. 207-216
Paper    Slides

J. Boutellier, V. Sadhanala, C. Lucarz, P. Brisk, and M. Mattavelli
Scheduling of Dataflow Models within the Reconfigurable Video Coding Framework
Poster / Full Paper

IEEE Workshop on Signal Processing Systems (SiPS)
Washington D. C., USA, October 8-10, 2008, pp. 182-187
Paper    Poster

A. K. Verma, P. Brisk, and P. Ienne
Dataflow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
27(10):1761-1774, October 2008
Paper

T. Massey, F. Dabiri, R. Jafari, H. Noshadi, P. Brisk, and M. Sarrafzadeh
Reconfigurable Medical Embedded Systems
in A. Lazakidou and K. Siassiakos, eds.
Handbook of Research on Distributed Medical Informatics and E-Health
IGI Global, August 22, 2008
Purchase the book

A. K. Verma, P. Brisk, and P. Ienne
XP2: A New compact Representation for Manipulating Arithmetic Circuits
17th International Workshop on Logic and Synthesis (IWLS)
Lake Tahoe, CA, USA, June 4-6, 2008
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Variable Latency Speculative Adder: A New Paradigm for Arithmetic Circuit Design
Design Automation and Test in Europe (DATE)
Munich, Germany, March 10-14, 2008, pp. 1250-1255
Paper     Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Design Automation and Test in Europe (DATE)
Munich, Germany, March 10-14, 2008, pp. 1256-1261
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
A Novel FPGA Logic Block for Improved Arithmetic Performance
16th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 24-26, 2008, pp. 171-180
Paper    Slides

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Architectural Improvement for Field Programmable Counter Arrays:
Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs

16th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 24-26, 2008, pp. 181-190
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Fast, Quasi-Optimal and Pipelined Instruction Set Extensions
13th Asia and South Pacific Design Automation Conference (ASPDAC)
Seoul, Korea, January 21-24, 2008, pp. 334-339
Paper    Slides

H. Paradeh-Afshar, P. Brisk, and P. Ienne
Efficient Synthesis of Compressor Trees on FPGAs
13th Asia and South Pacific Design Automation Conference (ASPDAC)
Seoul, Korea, January 21-24, 2008, pp. 138-143
Paper    Slides


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