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Philip Brisk: 2009 Publications


Nice, Beach                             Nice, Beach

2009

H. Parandeh-Afshar, A. Cevrero, P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne
A Flexible DSP Block to Enhance FPGA Arithmetic Performance
International Conference on Field Programmable Technology (FPT)
Sydney, Australia, December 9-11, 2009, pp. 70-77
Paper    Slides

A. K. Verma, P. Brisk, and P. Ienne
Iterative Layering: Optimizing Arithmetic Circuits By Structuring the Information Flow
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 2-5, 2009, pp. 797-804
Paper    Slides

P. Athanasopoulos, P. Brisk, Y. Leblebici, and P. Ienne
Memory Organization and Data Layout for Custom Instruction Set Extensions with Architecturally Visible Storage
International Conference on Computer-Aided Design (ICCAD)
San Jose, CA, USA, November 2-5, 2009, pp. 689-696
Paper    Slides

J. Boutellier, A. Cevrero, P. Brisk, and P. Ienne
Architectural Support for the Orchestration of Fine-Grained Multiprocessing for Portable Streaming Applications
IEEE Workshop on Signal Processing Systems (SiPS)
Tampere, Finland, October 7-9, 2009, pp. 115-120
Paper    Slides

A. Nahapetian, P. Brisk, S. Ghiasi, and M. Sarrafzadeh
An Approximation Algorithm for Scheduling on Heterogeneous Reconfigurable Resources
ACM Transactions on Embedded Computing Systems (TECS)
9(1): article #5, October, 2009
Paper

F. Regazzoni, A. Cevrero, F-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Workshop on Crytographic Hardware and Embedded Systems (CHES)
Lausanne, Switzerland, September 6-9, 2009, pp. 205-219
Paper    Slides

H. Parandeh-Afshar, P. Brisk, and P. Ienne
An FPGA Logic Cell Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2(3): article #19, September, 2009
Paper

H. Parandeh-Afshar, P. Brisk, and P. Ienne
Exploiting Fast Carry-Chains of FPGAs for Designing Compressor Trees
Michal Servit Best Paper Award

19th International Conference on Field-Programmable Logic and Applications (FPL)
Prague, Czech Republic, August 31 - September 2, 2009, pp. 242-249
Paper     Slides

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne
Using 3D Integration Technology to Realize Multi-Context FPGAs
Poster / Short Paper

19th International Conference on Field-Programmable Logic and Applications (FPL)
Prague, Czech Republic, August 31 - September 2, 2009 pp. 507-510
Paper    Poster

A. K. Verma, P. Brisk, and P. Ienne
A Decomposition Algorithm to Structure Arithmetic Circuits
18th International Workshop on Logic and Synthesis (IWLS)
Berkeley, CA, USA, July 31 - August 2, 2009
Paper    Slides

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
Way Stealing: Cache-Assisted Automatic Instruction Set Extensions
HiPEAC Paper Award

46th Design Automation Conference (DAC)
San Francisco, CA, USA, July 26-31, 2009, pp. 31-36
Paper    Slides

 J. L. Ayala, D. Atienza, and P. Brisk
Thermal-Aware Data Flow Analysis
Wild and Crazy Idea (WACI) / Short Paper

46th Design Automation Conference (DAC)
San Francisco, CA, USA, July 26-31, 2009, pp. 613-614
Paper    Slides

A. K. Verma, Y. Zhu, P. Brisk, and P. Ienne
Arithmetic Optimization for Custom Instruction Set Synthesis
Poster / Short Paper

7th IEEE Symposium on Application-Specific Processors (SASP)
San Francisco, CA, USA, July 27-28, 2009, pp. 54-57
Paper    Poster

M. Zuluaga, T. Kluter, P. Brisk, N. Topham, and P. Ienne
Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions
7th IEEE Symposium on Application-Specific Processors (SASP)
San Francisco, CA, USA, July 27-28, 2009, pp. 114-121
Paper    Slides

B. Boissinot, P. Brisk, A. Darte, and F. Rastello
SSI Revisited
Technical Report LIP-2009-24, ENS-Lyon
July 25, 2009
Paper

 A. K. Verma, P. Brisk, and P. Ienne
Challenges in Automatic Optimization of Arithmetic Circuits
Invited Paper

19th IEEE Symposium on Computer Arithmetic (ARITH-19)
Portland, OR, USA, June 8-10, 2009, pp. 213-218
Paper    Slides

P. Brisk, A. K. Verma, and P. Ienne
Optimistic Chordal Coloring: A Coalescing Heuristic for SSA Form Programs
Springer Journal on Design Automation for Embedded Systems (DAEM)
Special Issue: Embedded Systems Week 2007
13(1-2):115-137, June, 2009
Paper

 A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, H. S. A. Niaki,
C. Nicopoulos, F. K. Gurkaynak, Y. Leblebici, and P. Ienne
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
2(2): article #13, June 2009
Paper

A. Paidimarri, A. Cevrero, P. Brisk, and P. Ienne
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation
Poster / Short Paper
HiPEAC Paper Award

17th IEEE Symposium on Field-programmable Custom Computing Machines (FCCM)
Napa, CA, USA, April 5-7, 2009, pp. 267-270
Paper    Poster

P. Brisk and P. Ienne
On the Complexity of the Port Assignment Problem for Binary Commutative Operators in High-Level Synthesis
Poster / Full Paper

International Symposium on VLSI Design Automation and Test (VLSI-DAT)
Hsinchu, Taiwan, April 28-30, 2009, pp. 339-342
Paper    Poster

H. Parandeh-Afshar, P. Brisk, and P. Ienne
Scalable and Low Cost Design Approach for Variable Block Size Motion Estimation (VBSME)
International Symposium on VLSI Design Automation and Test (VLSI-DAT)
Hsinchu, Taiwan, April 28-30, 2009, pp. 271-274
Paper    Slides

A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne
3D Configuration Caching for 2D FPGAs
Poster / Abstract Only

17th International Symposium on FPGAs (FPGA)
Monterey, CA, USA, February 22-24, 2009, pp. 286
Poster

T. Kluter, P. Brisk, E. Charbon, and P. Ienne
MPSoC Design Using Application-Specific Architecturally Visible Communication
4th International Conference on High-Performance Embedded Architecture and Compilers (HiPEAC)
Paphos, Cyprus, January 25-28, 2009, pp. 183-197
Paper    Slides

A. Verma, A. K. Verma, P. Brisk, and P. Ienne
Hybrid LZA: A Near Optimal Implementation of the Leading Zero Anticipator
14th Asia and South Pacific Design Automation Conference (ASPDAC)
Yokohama, Japan, January 19-22, 2009, pp. 203-209
Paper    Slides


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